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LT3023 Dual 100mA, Low Dropout, Low Noise, Micropower Regulator
FEATURES
s s s s s s s s s
DESCRIPTIO
s s s s s
Low Noise: 20VRMS (10Hz to 100kHz) Low Quiescent Current: 20A/Channel Wide Input Voltage Range: 1.8V to 20V Output Current: 100mA/Channel Very Low Shutdown Current: <0.1A Low Dropout Voltage: 300mV at 100mA Adjustable Output from 1.22V to 20V Stable with 1F Output Capacitor Stable with Aluminum, Tantalum or Ceramic Capacitors Reverse Battery Protected No Reverse Current No Protection Diodes Needed Overcurrent and Overtemperature Protected Thermally Enhanced 10-Lead MSOP and DFN Packages
APPLICATIO S
s s s s s
Cellular Phones Pagers Battery-Powered Systems Frequency Synthesizers Wireless Modems
The LT (R)3023 is a dual, micropower, low noise, low dropout regulator. With an external 0.01F bypass capacitor, output noise drops to 20VRMS over a 10Hz to 100kHz bandwidth. Designed for use in battery-powered systems, the low 20A quiescent current per channel makes it an ideal choice. In shutdown, quiescent current drops to less than 0.1A. Shutdown control is independent for each channel, allowing for flexibility in power management. The device is capable of operating over an input voltage from 1.8V to 20V, and can supply 100mA of output current from each channel with a dropout voltage of 300mV. Quiescent current is well controlled in dropout. The LT3023 regulator is stable with output capacitors as low as 1F. Small ceramic capacitors can be used without the series resistance required by other regulators. Internal protection circuitry includes reverse battery protection, current limiting, thermal limiting and reverse current protection. The device is available as an adjustable device with a 1.22V reference voltage. The LT3023 regulator is available in the thermally enhanced 10-lead MSOP and DFN packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
VIN 3.7V TO 20V IN 1F SHDN1 SHDN2 BYP1 ADJ1 OUT1
3.3V/2.5V Low Noise Regulators 10Hz to 100kHz Output Noise
3.3V AT100mA 20VRMS NOISE 0.01F 422k 10F
LT3023 OUT2 0.01F BYP2 ADJ2 GND
249k 2.5V AT100mA 20VRMS NOISE 10F
VOUT 100V/DIV
261k
249k
3023 TA01
U
20VRMS
3023 TA01b
U
U
3023f
1
LT3023
ABSOLUTE AXI U RATI GS
IN Pin Voltage ........................................................ 20V OUT1, OUT2 Pin Voltage ....................................... 20V Input to Output Differential Voltage ....................... 20V ADJ1, ADJ2 Pin Voltage ......................................... 7V BYP1, BYP2 Pin Voltage ....................................... 0.6V SHDN1, SHDN2 Pin Voltage ................................. 20V
PACKAGE/ORDER I FOR ATIO
TOP VIEW BYP2 ADJ2 GND ADJ1 BYP1 1 2 3 4 5 11 10 OUT2 9 SHDN2 8 IN 7 SHDN1 6 OUT1
ORDER PART NUMBER LT3023EDD
BYP2 ADJ2 GND ADJ1 BYP1 1 2 3 4 5
DD PACKAGE 10-LEAD (3mm x 3mm) PLASTIC DFN EXPOSED PAD (PIN 11) IS GND MUST BE SOLDERED TO PCB TJMAX = 125C, JA = 40C/ W, JC = 10C/ W
DD PART MARKING LAJA
Consult factory for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. (Note 2)
PARAMETER Minimum Input Voltage (Notes 3, 11) ADJ1, ADJ2 Pin Voltage (Note 3, 4) Line Regulation (Note 3) Load Regulation (Note 3) Dropout Voltage VIN = VOUT(NOMINAL) (Notes 5, 6, 11) CONDITIONS ILOAD = 100mA VIN = 2V, ILOAD = 1mA 2.3V < VIN < 20V, 1mA < ILOAD < 100mA VIN = 2V to 20V, ILOAD = 1mA VIN = 2.3V, ILOAD = 1mA to 100mA VIN = 2.3V, ILOAD = 1mA to 100mA ILOAD = 1mA ILOAD = 1mA ILOAD = 10mA ILOAD = 10mA ILOAD = 50mA ILOAD = 50mA ILOAD = 100mA ILOAD = 100mA
q
2
U
U
W
WW U
W
(Note 1)
Output Short-Circut Duration .......................... Indefinite Operating Junction Temperature Range (Note 2) ............................................ - 40C to 125C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
TOP VIEW 10 9 8 7 6 OUT2 SHDN2 IN SHDN1 OUT1
ORDER PART NUMBER LT3023EMSE
11
MSE PACKAGE 10-LEAD PLASTIC MSOP EXPOSED PAD (PIN 11) IS GND MUST BE SOLDERED TO PCB TJMAX = 150C, JA = 40C/ W, JC = 10C/ W
MSE PART MARKING LTAHZ
MIN
TYP 1.8
MAX 2.3 1.235 1.250 10 12 25 0.15 0.19 0.22 0.29 0.28 0.38 0.35 0.45
UNITS V V V mV mV mV V V V V V V V V
q q q
1.205 1.190
1.220 1.220 1 1 0.10
q
0.17
q
0.24
q
0.30
q
3023f
LT3023
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. (Note 2)
PARAMETER GND Pin Current (Per Channel) VIN = VOUT(NOMINAL) (Notes 5, 7) CONDITIONS ILOAD = 0mA ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA ILOAD = 100mA COUT = 10F, CBYP = 0.01F, ILOAD = 100mA, BW = 10Hz to 100kHz (Notes 3, 8) VOUT = Off to On VOUT = On to Off VSHDN = 0V VSHDN = 20V VIN = 6V, VSHDN = 0V (Both SHDN Pins) VIN = 2.72V (Avg), VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz, ILOAD = 50mA VIN = 7V, VOUT = 0V VIN = 2.3V, VOUT = - 5% VIN = - 20V, VOUT = 0V
q q q q q q q q q q q
MIN
TYP 20 55 230 1 2.2 20 30
MAX 45 100 400 2 4 100 1.4 0.5 3 0.1
UNITS A A A mA mA VRMS nA V V A A A dB mA mA
Output Voltage Noise ADJ1/ADJ2 Pin Bias Current Shutdown Threshold SHDN1/SHDN2 Pin Current (Note 9) Quiescent Current in Shutdown Ripple Rejection (Note 3) Current Limit Input Reverse Leakage Current
0.25
0.8 0.65 0 1 0.01
55
65 200
110 1 5 10
mA A
Reverse Output Current (Notes 3,10) VOUT = 1.22V, VIN < 1.22V Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT3023 regulator is tested and specified under pulse load conditions such that TJ TA. The LT3023 is 100% production tested at TA = 25C. Performance at - 40C and 125C is assured by design, characterization and correlation with statistical process controls. Note 3: The LT3023 is tested and specified for these conditions with the ADJ1/ADJ2 pin connected to the corresponding OUT1/OUT2 pin. Note 4: Operating conditions are limited by maximum junction temperature. The regulated output voltage specification will not apply for all possible combinations of input voltage and output current. When operating at maximum input voltage, the output current range must be limited. When operating at maximum output current, the input voltage range must be limited. Note 5: To satisfy requirements for minimum input voltage, the LT3023 is tested and specified for these conditions with an external resistor divider (two 250k resistors) for an output voltage of 2.44V. The external resistor divider will add a 5A DC load on the output.
Note 6: Dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output current. In dropout, the output voltage will be equal to: VIN - VDROPOUT. Note 7: GND pin current is tested with VIN = 2.44V and a current source load. This means the device is tested while operating in its dropout region or at the minimum input voltage specification. This is the worst-case GND pin current. The GND pin current will decrease slightly at higher input voltages. Note 8: ADJ1 and ADJ2 pin bias current flows into the pin. Note 9: SHDN1 and SHDN2 pin current flows into the pin. Note 10: Reverse output current is tested with the IN pin grounded and the OUT pin forced to the rated output voltage. This current flows into the OUT pin and out the GND pin. Note 11: For the LT3023 dropout voltage will be limited by the minimum input voltage specification under some output voltage/load conditions. See the curve of Minimum Input Voltage in the Typical Performance Characteristics.
3023f
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LT3023 TYPICAL PERFOR A CE CHARACTERISTICS
Typical Dropout Voltage
500 450
DROPOUT VOLTAGE (mV) DROPOUT VOLTAGE (mV)
350 300 250 200 150 100 50 0 0
TJ = 125C
350 300 250 200 150 100 50 0
TJ 125C TJ 25C
DROPOUT VOLTAGE (mV)
400
TJ = 25C
10 20 30 40 50 60 70 80 90 100 OUTPUT CURRENT (mA)
3023 G01
Quiescent Current
40 35 VIN = 6V RL = 250k IL = 5A 1.240 1.235
QUIESCENT CURRENT (A)
ADJ PIN VOLTAGE (V)
30 25 VSHDN = VIN 20 15 10 5 0 -50 -25 VSHDN = 0V 0 25 50 75 100 125 TEMPERATURE (C)
3023 G03
1.230 1.225 1.220 1.215 1.210 1.205 1.200 -50 -25 0 25 50 75 100 125
QUIESCENT CURRENT (A)
GND Pin Current
2.50 2.25
GND PIN CURRENT (mA)
TJ = 25C *FOR VOUT = 1.22V
SHDN PIN THRESHOLD (V)
GND PIN CURRENT (mA)
2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 0 1 2
RL = 12.2 IL = 100mA*
RL = 24.4 IL = 50mA*
RL = 1.22k IL = 1mA*
RL = 122 IL = 10mA* 8 9 10
34567 INPUT VOLTAGE (V)
4
UW
3023 G07
Guaranteed Dropout Voltage
500 450 400
500
Dropout Voltage
450 400 350 300 250 200 150 100 50 IL = 50mA IL = 10mA IL = 1mA IL = 100mA
= TEST POINTS
0
10 20 30 40 50 60 70 80 90 100 OUTPUT CURRENT (mA)
3023 G02
0 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
3023 G03
ADJ1 or ADJ2 Pin Voltage
30
IL = 1mA
Quiescent Current
TJ = 25C RL = 250k IL = 5A VSHDN = VIN
25 20 15 10 5
VSHDN = 0V 0 0 2 4
TEMPERATURE (C)
3023 G05
6 8 10 12 14 16 18 20 INPUT VOLTAGE (V)
3023 G06
GND Pin Current vs ILOAD
2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT CURRENT (mA)
3023 G08
SHDN1 or SHDN2 Pin Threshold (On-to-Off)
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 50 0 75 25 TEMPERATURE (C) 100 125 IL = 1mA
VIN = VOUT(NOMINAL) + 1V
3023 G09
3023f
LT3023 TYPICAL PERFOR A CE CHARACTERISTICS
SHDN1 or SHDN2 Pin Threshold (Off-to-On)
1.0 0.9
SHDN PIN THRESHOLD (V)
1.0 0.9
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25
IL = 100mA
SHDN PIN INPUT CURRENT (A)
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
SHDN PIN INPUT CURRENT (A)
IL = 1mA
50 0 75 25 TEMPERATURE (C)
ADJ1 or ADJ2 Pin Bias Current
100 90
ADJ PIN BIAS CURRENT (nA)
80 70 60 50 40 30 20 10 0 -50 -25 50 0 75 25 TEMPERATURE (C) 100 125
SHORT-CIRCUIT CURRENT (mA)
250 200 150 100 50 0 0 1 4 3 2 5 INPUT VOLTAGE (V) 6 7
3023 G14
CURRENT LIMIT (mA)
Reverse Output Current
100
REVERSE OUTPUT CURRENT (A)
REVERSE OUTPUT CURRENT (A)
12 9 6 3 0 -50 -25
RIPPLE REJECTION (dB)
TA = 25C 90 VIN = 0V = VADJ V 80 OUT CURRENT FLOWS 70 INTO OUTPUT PIN 60 50 40 30 20 10 0 0 1 2 345678 OUTPUT VOLTAGE (V) 9 10
UW
100
3023 G10
3023 G13 3023 G16
SHDN1 or SHDN2 Pin Input Current
1.4
SHDN1 or SHDN2 Pin Input Current
VSHDN = 20V 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25
125
0 0 1 2 345678 SHDN PIN VOLTAGE (V) 9 10
50 25 0 75 TEMPERATURE (C)
100
125
3023 G11
3023 G12
Current Limit
350 300 VOUT = 0V TJ = 25C 350 300 250 200 150 100 50
Current Limit
VIN = 7V VOUT = 0V
0 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
3023 G15
Reverse Output Current
18 15 VIN = 0V VOUT = VADJ = 1.22V
Input Ripple Rejection
80 70 60 50 40 30 20 IL = 100mA 10 V = 2.3V + 50mV IN RMS RIPPLE COUT = 1F CBYP = 0 0 0.1 100 0.01 1 10 1000 FREQUENCY (kHz)
LTXXXX GXX
COUT = 10F
50 25 75 0 TEMPERATURE (C)
100
125
3023 G17
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5
LT3023 TYPICAL PERFOR A CE CHARACTERISTICS
Input Ripple Rejection
80 70
RIPPLE REJECTION (dB) 80
CBYP = 0.01F CBYP = 1000pF CBYP = 100pF
60 50 40 30 20 IL = 100mA 10 V = 2.3V + 50mV IN RMS RIPPLE COUT = 10F 0 0.1 0.01 1 10 FREQUENCY (kHz)
RIPPLE REJECTION (dB)
Channel-to-Channel Isolation
100
CHANNEL-TO-CHANNEL ISOLATION (dB)
90 80 70 60 50 40 30 20 10 0 0.01 0.1
ILOAD = 100mA PER CHANNEL MINIMUM INPUT VOLTAGE (V)
IL = 100mA 1.5 IL = 50mA 1.0
LOAD REGULATION (mV)
1 10 FREQUENCY (kHz)
Output Noise Spectral Density
OUTPUT NOISE SPECTRAL DENSITY (V/Hz)
10
OUTPUT NOISE SPECTRAL DENSITY (V/Hz)
COUT = 10F CBYP = 0 IL = 100mA VOUT SET FOR 5V VOUT =VADJ
1
CBYP = 1000pF CBYP = 100pF
1
OUTPUT NOISE (VRMS)
0.1
0.01 0.01
0.1
1 10 FREQUENCY (kHz)
6
UW
100
3023 G19
Input Ripple Rejection
70 60 50 40 30 20 10 VIN = VOUT (NOMINAL) + 1V + 0.5VP-P RIPPLE AT f = 120Hz IL = 50mA 0 25 50 75 100 125
Channel-to-Channel Isolation
VOUT1 20mV/DIV
VOUT2 20mV/DIV
1000
0 -50 -25
TEMPERATURE (C)
3023 G20
50s/DIV COUT1, COUT2 = 10F CBYP1, CBYP2 = 0.01F IL1 = 10mA to 100mA IL2 = 10mA to 100mA VIN = 6V, VOUT1 = VOUT2 = 5V
3023 G21a
Minimum Input Voltage
2.5
0 -1
Load Regulation
2.0
-2 -3 -4 -5 -6 -7 -8 -9 IL = 1mA TO 100mA -10 0 50 75 25 -50 -25 TEMPERATURE (C)
0.5
100
1000
3023 G21b
0 -50 -25
50 0 75 25 TEMPERATURE (C)
100
125
100
125
3023 G22
3023 G23
Output Noise Spectral Density
10
RMS Output Noise vs Bypass Capacitor
160 140 120 100 80 60 40 VOUT =VADJ 20 VOUT SET FOR 5V COUT = 10F IL = 100mA f = 10Hz TO 100kHz
COUT = 10F IL = 100mA VOUT SET FOR 5V
VOUT =VADJ 0.1 CBYP = 0.01pF
100
3023 G24
0.01 0.01
0
0.1 1 10 FREQUENCY (kHz) 100
3023 G25
10
100 CBYP (pF)
1k
10k
3023 G26
3023f
LT3023 TYPICAL PERFOR A CE CHARACTERISTICS
RMS Output Noise vs Load Current (10Hz to 100kHz)
160 140 COUT = 10F CBYP = 0F CBYP = 0.01F VOUT SET FOR 5V
OUTPUT NOISE (VRMS)
120 100 80 60 40 20 0 0.01
VOUT =VADJ
VOUT SET FOR 5V VOUT =VADJ 0.1 1 10 LOAD CURRENT (mA) 100
3023 G27
10Hz to 100kHz Output Noise CBYP = 1000pF
VOUT 100V/DIV
1ms/DIV COUT = 10F IL = 100mA VOUT SET FOR 5V OUT
Transient Response CBYP = 0
OUTPUT VOLTAGE DEVIATION (V) OUTPUT VOLTAGE DEVIATION (V) 0.2 0.1 0 -0.1 -0.2 VIN = 6V CIN = 10F COUT = 10F VOUT SET FOR 5V OUT 0.04 0.02 0 -0.02 -0.04
LOAD CURRENT (mA)
100 50 0 0 400 800
LOAD CURRENT (mA)
UW
10Hz to 100kHz Output Noise CBYP = 0
10Hz to 100kHz Output Noise CBYP = 100pF
VOUT 100V/DIV
VOUT 100V/DIV
1ms/DIV COUT = 10F IL = 100mA VOUT SET FOR 5V OUT
3023 G28
1ms/DIV COUT = 10F IL = 100mA VOUT SET FOR 5V OUT
3023 G29
10Hz to 100kHz Output Noise CBYP = 0.01F
VOUT 100V/DIV
3023 G30
1ms/DIV COUT = 10F IL = 100mA VOUT SET FOR 5V OUT
3023 G31
Transient Response CBYP = 0.01F
VIN = 6V CIN = 10F COUT = 10F VOUT SET FOR 5V OUT
100 50 0 0 20 40 60 80 100 120 140 160 180 200 TIME (s)
3023 G33
1200 TIME (s)
1600
2000
3023 G32
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7
LT3023
PI FU CTIO S
GND (Pin 3): Ground. ADJ1/ADJ2 (Pins 4/2): Adjust Pin. These are the inputs to the error amplifiers. These pins are internally clamped to 7V. They have a bias current of 30nA which flows into the pin (see curve of ADJ1/ADJ2 Pin Bias Current vs Temperature in the Typical Performance Characteristics section). The ADJ1 and ADJ2 pin voltage is 1.22V referenced to ground and the output voltage range is 1.22V to 20V. BYP1/BYP2 (Pins 5/1): Bypass. The BYP1/BYP2 pins are used to bypass the reference of the LT3023 regulator to achieve low noise performance from the regulator. The BYP1/BYP2 pins are clamped internally to 0.6V (one VBE) from ground. A small capacitor from the corresponding output to this pin will bypass the reference to lower the output voltage noise. A maximum value of 0.01F can be used for reducing output voltage noise to a typical 20VRMS over a 10Hz to 100kHz bandwidth. If not used, this pin must be left unconnected. OUT1/OUT2 (Pins 6/10): Output. The outputs supply power to the loads. A minimum output capacitor of 1F is required to prevent oscillations. Larger output capacitors will be required for applications with large transient loads to limit peak voltage transients. See the Applications Information section for more information on output capacitance and reverse output characteristics. SHDN1/SHDN2 (Pins 7/9): Shutdown. The SHDN1/SHDN2 pins are used to put the corresponding channel of the LT3023 regulator into a low power shutdown state. The output will be off when the pin is pulled low. The SHDN1/SHDN2 pins can be driven either by 5V logic or open-collector logic with pull-up resistors. The pull-up resistors are required to supply the pull-up current of the open-collector gates, normally several microamperes, and the SHDN1/SHDN2 pin current, typically 1A. If unused, the pin must be connected to VIN. The device will not function if the SHDN1/SHDN2 pins are not connected. IN (Pin 8): Input. Power is supplied to the device through the IN pin. A bypass capacitor is required on this pin if the device is more than six inches away from the main input filter capacitor. In general, the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-powered circuits. A bypass capacitor in the range of 1F to 10F is sufficient. The LT3023 regulator is designed to withstand reverse voltages on the IN pin with respect to ground and the OUT pin. In the case of a reverse input, which can happen if a battery is plugged in backwards, the device will act as if there is a diode in series with its input. There will be no reverse current flow into the regulator and no reverse voltage will appear at the load. The device will protect both itself and the load. Exposed Pad (Pin 11): Ground. This pin must be soldered to the PCB and electrically connected to ground.
8
U
U
U
3023f
LT3023
APPLICATIO S I FOR ATIO
The LT3023 is a dual 100mA low dropout regulator with micropower quiescent current and shutdown. The device is capable of supplying 100mA per channel at a dropout voltage of 300mV. Output voltage noise can be lowered to 20VRMS over a 10Hz to 100kHz bandwidth with the addition of a 0.01F reference bypass capacitor. Additionally, the reference bypass capacitor will improve transient response of the regulator, lowering the settling time for transient load conditions. The low operating quiescent current (20A per channel) drops to less than 1A in shutdown. In addition to the low quiescent current, the LT3023 regulator incorporates several protection features which make it ideal for use in battery-powered systems. The device is protected against both reverse input and reverse output voltages. In battery backup applications where the output can be held up by a backup battery when the input is pulled to ground, the LT3023 acts like it has a diode in series with its output and prevents reverse current flow. Additionally, in dual supply applications where the regulator load isreturned to a negative supply, the output can be pulled below ground by as much as 20V and still allow the device to start and operate. Adjustable Operation The LT3023 has an output voltage range of 1.22V to 20V. The output voltage is set by the ratio of two external resistors as shown in Figure 1. The device servos the output to maintain the corresponding ADJ1/ADJ2 pin voltage at 1.22V referenced to ground. The current in R1 is then equal to 1.22V/R1 and the current in R2 is the current in R1 plus the ADJ1/ADJ2 pin bias current. The ADJ1/ADJ2 pin bias current, 30nA at 25C, flows through R2 into the ADJ1/ADJ2 pin. The output voltage can be calculated using the formula in Figure 1. The value of R1 should be no greater than 250k to minimize errors in the output voltage caused by the ADJ1/ ADJ2 pin bias current. Note that in shutdown the output is turned off and the divider current will be zero. Curves of ADJ1/ADJ2 Pin Voltage vs Temperature and ADJ1/ADJ2 Pin Bias Current vs Temperature appear in the Typical Performance Characteristics.
U
IN VIN OUT1/OUT2 VOUT
W
UU
+
LT3023 ADJ1/ADJ2 GND R1
3023 F01
R2
R2 VOUT = 1.22V 1 + + IADJ R2 R1 VADJ = 1.22V IADJ = 30nA AT 25C
( )( )
OUTPUT RANGE = 1.22V TO 20V
Figure 1. Adjustable Operation
The device is tested and specified with the ADJ1/ADJ2 pin tied to the corresponding OUT1/OUT2 pin for an output voltage of 1.22V. Specifications for output voltages greater than 1.22V will be proportional to the ratio of the desired output voltage to 1.22V: VOUT/1.22V. For example, load regulation for an output current change of 1mA to 100mA is -1mV typical at VOUT = 1.22V. At VOUT = 12V, load regulation is: (12V/1.22V)(-1mV) = - 9.8mV Bypass Capacitance and Low Noise Performance The LT3023 regulator may be used with the addition of a bypass capacitor from VOUT to the corresponding BYP1/ BYP2 pin to lower output voltage noise. A good quality low leakage capacitor is recommended. This capacitor will bypass the reference of the regulator, providing a low frequency noise pole. The noise pole provided by this bypass capacitor will lower the output voltage noise to as low as 20VRMS with the addition of a 0.01F bypass capacitor. Using a bypass capacitor has the added benefit of improving transient response. With no bypass capacitor and a 10F output capacitor, a 10mA to 100mA load step will settle to within 1% of its final value in less than 100s. With the addition of a 0.01F bypass capacitor, the output will stay within 1% for a 10mA to 100mA load step (see Transient Reponse in Typical Performance Characteristics section). However, regulator start-up time is inversely proportional to the size of the bypass capacitor, slowing to 15ms with a 0.01F bypass capacitor and 10F output capacitor.
3023f
9
LT3023
APPLICATIO S I FOR ATIO
Output Capacitance and Transient Response The LT3023 regulator is designed to be stable with a wide range of output capacitors. The ESR of the output capacitor affects stability, most notably with small capacitors. A minimum output capacitor of 1F with an ESR of 3 or less is recommended to prevent oscillations. The LT3023 is a micropower device and output transient response will be a function of output capacitance. Larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. Bypass capacitors, used to decouple individual components powered by the LT3023, will increase the effective output capacitor value. With larger capacitors used to bypass the reference (for low noise operation), larger values of output capacitors are needed. For 100pF of bypass capacitance, 2.2F of output capacitor is recommended. With a 330pF bypass capacitor or larger, a 3.3F output capacitor is recommended. The shaded region of Figure 2 defines the region over which the LT3023 regulator is stable. The minimum ESR needed is defined by the amount of bypass capacitance used, while the maximum ESR is 3. Extra consideration must be given to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. The most common
4.0
CHANGE IN VALUE (%)
3.5 CHANGE IN VALUE (%) 3.0 STABLE REGION 2.5
ESR ()
2.0 1.5 1.0 0.5 0 1 3 2 4 5 6 7 8 9 10 OUTPUT CAPACITANCE (F)
3023 F02
CBYP = 0 CBYP = 100pF CBYP = 330pF CBYP > 3300pF
Figure 2. Stability
10
U
dielectrics used are Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are good for providing high capacitances in a small package, but exhibit strong voltage and temperature coefficients as shown in Figures 3 and 4. When used with a 5V regulator, a 10F Y5V capacitor can exhibit an effective value as low as 1F to 2F over the operating temperature range. The X5R and X7R dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and is available in higher values.
20 0 X5R -20 -40 -60 Y5V -80 -100 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10F 0 2 4 8 6 10 12 DC BIAS VOLTAGE (V) 14 16
3023 F03
W
UU
Figure 3. Ceramic Capacitor DC Bias Characteristics
40 20 0 -20 -40 -60 -80 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10F 50 25 75 0 TEMPERATURE (C) 100 125 Y5V X5R
-100 -50 -25
3023 F04
Figure 4. Ceramic Capacitor Temperature Characteristics
3023f
LT3023
APPLICATIO S I FOR ATIO
Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or microphone works. For a ceramic capacitor the stress can be induced by vibrations in the system or thermal transients. The resulting voltages produced can cause appreciable amounts of noise, especially when a ceramic capacitor is used for noise bypassing. A ceramic capacitor produced Figure 5's trace in response to light tapping from a pencil. Similar vibration induced behavior can masquerade as increased output voltage noise.
COUT = 10F CBYP = 0.01F ILOAD = 100mA VOUT 500V/DIV
100ms/DIV
3023 F05
Figure 5. Noise Resulting from Tapping on a Ceramic Capacitor
Thermal Considerations The power handling capability of the device will be limited by the maximum rated junction temperature (125C). The power dissipated by the device will be made up of two components (for each channel): 1. Output current multiplied by the input/output voltage differential: (IOUT)(VIN - VOUT), and 2. GND pin current multiplied by the input voltage: (IGND)(VIN). The ground pin current can be found by examining the GND Pin Current curves in the Typical Performance Characteristics section. Power dissipation will be equal to the sum of the two components listed above. Power
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dissipation from both channels must be considered during thermal analysis. The LT3023 regulator has internal thermal limiting designed to protect the device during overload conditions. For continuous normal conditions, the maximum junction temperature rating of 125C must not be exceeded. It is important to give careful consideration to all sources of thermal resistance from junction to ambient. Additional heat sources mounted nearby must also be considered. For surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper traces. Copper board stiffeners and plated through-holes can also be used to spread the heat generated by power devices. The following tables list thermal resistance for several different board sizes and copper areas. All measurements were taken in still air on 3/32" FR-4 board with one ounce copper.
Table 1. MSE Package, 10-Lead MSOP
COPPER AREA TOPSIDE* BACKSIDE 2500mm2 1000mm 100mm
2
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BOARD AREA 2500mm2 2500mm 2500mm
2
THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 40C/W 45C/W 50C/W 62C/W
2500mm2 2500mm 2500mm
2
225mm2
2
2500mm2
2
2500mm2
2
*Device is mounted on topside.
Table 2. DD Package, 10-Lead DFN
COPPER AREA TOPSIDE* BACKSIDE 2500mm2 1000mm 225mm 100mm
2 2 2
BOARD AREA 2500mm2 2500mm2 2500mm 2500mm
2 2
THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 40C/W 45C/W 50C/W 62C/W
2500mm2 2500mm 2500mm 2500mm
2 2 2
*Device is mounted on topside.
The thermal resistance juncton-to-case (JC), measured at the Exposed Pad on the back of the die is 10C/W.
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LT3023
APPLICATIONS INFORMATION
Calculating Junction Temperature Example: Given an output voltage on the first channel of 3.3V, an output voltage of 2.5V on the second channel, an input voltage range of 4V to 6V, output current ranges of 0mA to 100mA for the first channel and 0mA to 50mA for the second channel, with a maximum ambient temperature of 50C, what will the maximum junction temperature be? The power dissipated by each channel of the device will be equal to: IOUT(MAX)(VIN(MAX) - VOUT) + IGND(VIN(MAX)) where (for the first channel): IOUT(MAX) = 100mA VIN(MAX) = 6V IGND at (IOUT = 100mA, VIN = 6V) = 2mA so: P1 = 100mA(6V - 3.3V) + 2mA(6V) = 0.28W and (for the second channel): IOUT(MAX) = 50mA VIN(MAX) = 6V IGND at (IOUT = 50mA, VIN = 6V) = 1mA so: P2 = 50mA(6V - 2.5V) + 1mA(6V) = 0.18W The thermal resistance will be in the range of 40C/W to 60C/W depending on the copper area. So the junction temperature rise above ambient will be approximately equal to: (0.28W + 018W)(60C/W) = 27.8C The maximum junction temperature will then be equal to the maximum junction temperature rise above ambient plus the maximum ambient temperature or: TJMAX = 50C + 27.8C = 77.8C Protection Features The LT3023 regulator incorporates several protection features which makes it ideal for use in battery-powered circuits. In addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the devices are protected against reverse input voltages, reverse output voltages and reverse voltages from output to input. Current limit protection and thermal overload protection are intended to protect the device against current overload conditions at the output of the device. For normal operation, the junction temperature should not exceed 125C. The input of the device will withstand reverse voltages of 20V. Current flow into the device will be limited to less than 1mA (typically less than 100A) and no negative voltage will appear at the output. The device will protect both itself and the load. This provides protection against batteries which can be plugged in backward. The output of the LT3023 can be pulled below ground without damaging the device. If the input is left open circuit or grounded, the output can be pulled below ground by 20V. The output will act like an open circuit; no current will flow out of the pin. If the input is powered by a voltage source, the output will source the short-circuit current of the device and will protect itself by thermal limiting. In this case, grounding the SHDN1/SHDN2 pins will turn off the device and stop the output from sourcing the short-circuit current. The ADJ1 and ADJ2 pins can be pulled above or below ground by as much as 7V without damaging the device. If the input is left open circuit or grounded, the ADJ1 and ADJ2 pins will act like an open circuit when pulled below ground and like a large resistor (typically 100k) in series with a diode when pulled above ground. In situations where the ADJ1 and ADJ2 pins are connected to a resistor divider that would pull the pins above their 7V clamp voltage if the output is pulled high, the ADJ1/ADJ2 pin input current must be limited to less than 5mA. For example, a resistor divider is used to provide a regulated 1.5V output from the 1.22V reference when the output is forced to 20V. The top resistor of the resistor divider must be chosen to limit the current into the ADJ pin to less than 5mA when the ADJ1/ADJ2 pin is at 7V. The 13V difference between output and ADJ1/ADJ2 pin divided by the 5mA maximum current into the ADJ1/ADJ2 pin yields a minimum top resistor value of 2.6k.
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12
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LT3023
APPLICATIO S I FOR ATIO
REVERSE OUTPUT CURRENT (A)
In circuits where a backup battery is required, several different input/output conditions can occur. The output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left open circuit. Current flow back into the output will follow the curve shown in Figure 6. When the IN pin of the LT3023 is forced below the OUT1 or OUT2 pins or the OUT1/OUT2 pins are pulled above the IN pin, input current will typically drop to less than 2A. This can happen if the input of the device is connected to a discharged (low voltage) battery and the output is held up by either a backup battery or a second regulator circuit. The state of the SHDN1/SHDN2 pins will have no effect on the reverse output current when the output is pulled above the input.
TYPICAL APPLICATIO S
Noise Bypassing Slows Startup, Allows Outputs to Track
VIN 3.7V TO 20V 1F
IN
OUT1 0.01F BYP1 ADJ1 LT3023 249k 10F 422k
OFF ON
SHDN1 SHDN2 GND
OUT2 0.01F BYP2 ADJ2 249k 10F 261k
STARTUP TIME (ms)
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100 TA = 25C 90 VIN = 0V V = VADJ 80 OUT CURRENT FLOWS 760 INTO OUTPUT PIN 60 50 40 30 20 10 0 0 1 2 345678 OUTPUT VOLTAGE (V) 9 10
3023 F06
W
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Figure 6. Reverse Output Current
VSHDN1/SHDN2 1V/DIV VOUT1 1V/DIV VOUT2 1V/DIV 3.3V AT 100mA 2ms/DIV
3023 TA02b
Startup Time
2.5V AT 100mA 100
10
3023 TA02a
1
0.1 10 100 CBYP (pF)
3023 TA02c
1000
10000
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13
LT3023
PACKAGE DESCRIPTIO
3.50 0.05 1.65 0.05 2.15 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 6 0.38 0.10 10
PIN 1 TOP MARK (SEE NOTE 5) 5 0.200 REF 0.75 0.05 2.38 0.10 (2 SIDES) 1
NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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DD Package 10-Lead Plastic DFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1699)
0.675 0.05 3.00 0.10 (4 SIDES) 1.65 0.10 (2 SIDES)
(DD10) DFN 0403
0.25 0.05 0.50 BSC
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD
3023f
LT3023
PACKAGE DESCRIPTIO
2.794 0.102 (.110 .004)
5.23 (.206) MIN
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
0.254 (.010) GAUGE PLANE
0.18 (.007)
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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MSE Package 10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1663)
BOTTOM VIEW OF EXPOSED PAD OPTION
0.889 0.127 (.035 .005)
1
2.06 0.102 (.081 .004) 1.83 0.102 (.072 .004)
2.083 0.102 3.20 - 3.45 (.082 .004) (.126 - .136)
10 3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6
0.497 0.076 (.0196 .003) REF
4.90 0.152 (.193 .006) DETAIL "A" 0 - 6 TYP 12345 0.53 0.152 (.021 .006) DETAIL "A" SEATING PLANE 1.10 (.043) MAX
3.00 0.102 (.118 .004) (NOTE 4)
0.86 (.034) REF
0.17 - 0.27 (.007 - .011) TYP
0.50 (.0197) BSC
0.127 0.076 (.005 .003)
MSOP (MSE) 0603
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15
LT3023
TYPICAL APPLICATIO S
Startup Sequencing Turn-On Waveforms
VSHDN1 1V/DIV
VIN 3.7V TO 20V 1F
IN
OUT1 LT3023 BYP1 ADJ1 249k 28k 0.01F 422k 10F 35.7k
OFF ON
SHDN1 SHDN2
OUT2 0.01F BYP2 GND ADJ2 249k 261k 10F
0.47F
RELATED PARTS
PART NUMBER LT1129 LT1175 DESCRIPTION 700mA, Micropower, LDO 500mA, Micropower Negative LDO COMMENTS VIN: 4.2V to 30V, VOUT(MIN): 3.75V, IQ: 50A, ISD: 16A, DD, SOT-223, S8,TO220, TSSOP20 Packages Guaranteed Voltage Tolerance and Line/Load Regulation VIN: -20V to -4.3V, VOUT(MIN): -3.8V, IQ: 45A, ISD: 10A, DD,SOT-223, S8 Packages Accurate Programmable Current Limit, Remote Sense VIN: -35V to -4.2V, VOUT(MIN): -2.40V, IQ: 2.5mA, ISD: <1A, TO220-5 Package Low Noise < 20VRMS, Stable with 1F Ceramic Capacitors, VIN: 1.8V to 20V, VOUT(MIN): 1.22V, IQ: 20A, ISD: <1A, ThinSOT Package Low Noise < 20VRMS, VIN: 1.8V to 20V, VOUT(MIN): 1.22V, IQ: 25A, ISD: <1A, MS8 Package Low Noise < 20VRMS, VIN: 1.8V to 20V, VOUT(MIN): 1.22V, IQ: 30A, ISD: <1A, S8 Package Low Noise < 40VRMS, "A" Version Stable with Ceramic Capacitors, VIN: 2.7V to 20V, VOUT(MIN): 1.21V, IQ: 1mA, ISD: <1A, DD, TO220 Packages Low Noise < 30VRMS, Stable with 1F Ceramic Capacitors, VIN: 1.6V to 6.5V, VOUT(MIN): 1.25V, IQ: 40A, ISD: <1A, ThinSOT Package Low Noise < 20VRMS, VIN: 1.8V to 20V, VOUT(MIN): 1.22V, IQ: 30A, ISD: <1A, MS8 Package Low Noise < 40VRMS, "A" Version Stable with Ceramic Capacitors, VIN: 2.1V to 20V, VOUT(MIN): 1.21V, IQ: 1mA, ISD: <1A, DD, TO220, SOT-223, S8 Packages Low Noise < 30VRMS, Stable with Ceramic Capacitors, VIN: -0.9V to -20V, VOUT(MIN): -1.21V, IQ: 30A, ISD: 3A, ThinSOT Package VIN: 2.5V to 5.5V, VOUT(MIN): 0.6 V, IQ: 40A, ISD: <1A, MSE Package
3023f
LT1185 LT1761 LT1762 LT1763 LT1764/LT1764A LTC1844 LT1962 LT1963/LT1963A
3A, Negative LDO 100mA, Low Noise Micropower, LDO 150mA, Low Noise Micropower, LDO 500mA, Low Noise Micropower, LDO 3A, Low Noise, Fast Transient Response, LDO 150mA, Very Low Drop-Out LDO 300mA, Low Noise Micropower, LDO 1.5A, Low Noise, Fast Transient Response, LDO
LT1964 LTC3407
200mA, Low Noise Micropower, Negative LDO Dual 600mA. 1.5MHz Synchronous Step Down DC/DC Converter
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
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3.3V AT 100mA
VOUT1 1V/DIV VOUT2 1V/DIV
2.5V AT 100mA
2ms/DIV
3023 TA03b
Turn-Off Waveforms
VSHDN1 1V/DIV
3023 TA03a
VOUT1 1V/DIV VOUT2 1V/DIV
2ms/DIV
3023 TA03c
LT/TP 1103 1K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

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